1. Field of the Invention
The present invention relates to a matrix of EPROM memory cells with a tablecloth structure having an improved capacitive ratio, together with a process for its manufacture.
2. Description of the Related Art Including Information Disclosed under 37 C.F.R. .sctn.1.97-1.99
Matrices of EPROM memory cells are known having a so-called "tablecloth" structure with source and drain lines parallel and alternated one to another on a semiconductor substrate, floating gate areas interposed in a checkerboard pattern between said source and drain lines and control gate lines parallel to one another and perpendicular to said source and drain lines in a superimposed condition with intermediate dielectric and aligned with respect to said floating gate areas.
The tablecloth structures have the favourable distinction of ensuring very high levels of integration (from 4 to 16 Mbit) maintaining topographical layout rules which are accessibile with the current technology. Moreover, they allow the substantial reduction of the number of drain contacts in the matrix area (about 1/8th or 1/16 with respect to standard EPROM matrices) with appreciable benefits from the point of view of defectiveness.
Several tablecloth structures have so far been put forward, from the original one described in the U.S. Pat. No. 4,792,925 to the more recent one described in European Patent Application No. 0352830, both assigned to the present Assignee.
The first of such structures provides for the non-usage of field oxide for matrix insulation. It is in fact possible, starting from a flat active area, to insulate from one another the cells and the source and drain lines (constituting the "bit lines") by means of insulation systems of the P.sup.+ type, followed by the deposition of layers of dielectric materials and their subsequent planarization.
The greatest problem of this structure is represented by the low capacitive coupling between the control gate and the floating gate of each cell. In fact, the coupling area between the gates is practically identical to that between the floating gate and the substrate, so that, if similar thicknesses of oxide are used, the capacitive ratio is seen to assume a value near 0.5, that is lower than that of standard EPROM cells (normally between 0.6 and 0.7). This is too low a value for the cell to have good writing characteristics. Under these conditions the capacitive contribution due to the coupling of the floating gate towards the drain becomes heavier. The memory is consequently very sensitive to the so-called drain turn-on phenomenon, a parasitic phenomenon which can lead to soft-erasure phenomena of non-selected cells and in any case to the worsening of the writing characteristics.
The second structure mentioned above provides for the presence, in various configurations, of islands of field oxide in the matrix area. This allows the attainment of larger capacitive couplings between the floating gate and the control gate but at the expense of a greater complexity of accomplishment (high number of masks) and/or of a lower degree of obtainable integration.